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LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 LMH0031 smpte 292m/259m digital video deserializer / descrambler with video and ancillary data fifos check for samples: LMH0031 1 features applications 2 ? sdtv/hdtv serial digital video standard ? sdtv/hdtv serial-to-parallel digital video compliant interfaces for: ? supports 270 mbps, 360 mbps, 540 mbps, ? video editing equipment 1.483 gbps and 1.485 gbps serial video data ? vtrs rates with auto-detection ? standards converters ? lsb de-dithering option ? digital video routers and switchers ? uses low-cost 27mhz crystal or clock ? digital video processing and editing oscillator reference equipment ? fast vco lock time: < 500 s at 1.485 gbps ? video test pattern generators and digital ? built-in self-test (bist) and video test pattern video test equipment generator (tpg) ? video signal generators (1) patent applications made or pending description ? automatic edh/crc word and flag processing the LMH0031 smpte 292m / 259m digital video deserializer/descrambler with video and ancillary ? ancillary data fifo with extensive packet data fifos is a monolithic integrated circuit that handling options deserializes and decodes smpte 292m, 1.485gbps ? adjustable, 4-deep parallel output video data (or 1.483gbps) serial component video data, to 20-bit fifo parallel data with a synchronized parallel word-rate clock. it also deserializes and decodes smpte 259m, ? flexible control and configuration i/o port 270mbps, 360mbps and smpte 344m (proposed) ? lvcmos compatible control inputs and clock 540mbps serial component video data, to 10-bit and data outputs parallel data. functions performed by the LMH0031 ? lvds and ecl-compatible, differential, serial include: clock/data recovery from the serial data, inputs serial-to-parallel data conversion, smpte standard data decoding, nrzi-to-nrz conversion, parallel data ? 3.3v i/o power supply and 2.5v logic power clock generation, word framing, crc and edh data supply operation checking and handling, ancillary data extraction and ? low power: typically 850mw automatic video format determination. the parallel ? 64-pin tqfp package video output features a variable-depth fifo which can be adjusted to delay the output data up to 4 ? commercial temperature range 0 c to +70 c parallel data clock periods. ancillary data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip fifo. reverse lsb dithering is also implemented. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2006 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com description (continued) the unique multi-functional i/o port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. this feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. the LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. separate power pins for the pll, deserializer and other functional circuits improve power supply rejection and noise performance. the LMH0031 has a unique built-in self-test (bist) and video test pattern generator (tpg). the bist enables comprehensive testing of the device by the user. the bist uses the tpg as input data and includes sd and hd component video test patterns, reference black, pll and eq pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. the colour bar pattern has optional transition coding at changes in the chroma and luma bar data. the tpg data is output via the parallel data port. the lmh0030, smpte 292m / 259m digital video serializer with ancillary data fifo and integrated cable driver, is the ideal complement to the LMH0031. the LMH0031 ' s internal circuitry is powered from +2.5 volts and the i/o circuitry from a +3.3 volt supply. power dissipation is typically 850mw. the device is packaged in a 64-pin tqfp. typical application 2 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031 lmh0030 sd/hd encoder/ serializer/ cable driver lmh0034 adaptive cable equalizer 75 : coaxial cable 1 p f 75 : 1% smpte video data input smpte 292m or 259m serial data v dd LMH0031 sd/hd decoder/ deserializer parallel ancilliary data input smpte video data output parallel ancilliary data output 75 : 1% 1 p f
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 block diagram copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: LMH0031 trs & format detector configuration & control registers smpte nrzi-nrz converter descrambler/ deserializer edh / crc generators/checkers pll/clock system bist & tpg reset control framing control dv[9:0] reset sdi ancilliary data fifo multi-function i/o port dv[19:10] ad[9:0] anc / ctrl a clk rd / wr i/o[7:0] int. reset system master controller master bus de-dithering p clk video data fifo & output v clk p clk video data bus sdi sdi bias r bb r ref input data samplers clock/data recovery reference clock/oscillator xtali/ext clk xtalo p clk
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com connection diagram figure 1. 64-pin tqfp see package number pag0064a 4 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 11 10 9 8 7 6 5 4 3 2 1 LMH0031 48 47 46 45 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v ddd ad 0 ad 1 ad 2 ad 3 ad 4 ad 5 ad 6 ad 7 ad 8 ad 9 a clk v ssd io5 io6 io 7 v ddio v ssd dv10 dv11 dv12 dv13 dv14 dv15 dv16 dv17 dv18 dv19 io2 io3 io4 dv 0 dv 1 dv 2 dv 3 dv 4 dv 5 dv6 dv 7 dv8 dv9 io 1 io 0 v ssio v ddio v ddpll r v v vv v r bb reset rd/wr sspll anc/ctrl ddsi ddd ssio sssi sdi xtalo ref xtali/ext clk vclk sdi v ssd v ddd v ssio
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings (1) (2) cmos i/o supply voltage (v ddio ? v ssio ): 4.0v sdi supply voltage (v ddsi ? v sssi ): 4.0v digital logic supply voltage (v ddd ? v ssd ): 3.0v pll supply voltage (v ddpll ? v sspll ): 3.0v cmos input voltage (vi): v ssio ? 0.15v to v ddio +0.15v cmos output voltage (vo): v ssio ? 0.15v to v ddio +0.15v cmos input current (single input): vi = v ssio ? 0.15v: ? 5 ma vi = v ddio +0.15v: +5 ma cmos output source/sink current: cmos output source/sink current: 6 ma 6 ma i bb output current: +300 a i ref output current: +300 a sdi input voltage (vi): v sssi ? 0.15v to v ddsi +0.15v package thermal resistance ja @ 0 lfm airflow 40.1 c/w ja @ 500 lfm airflow 24.5 c/w jc 5.23 c/w storage temp. range: ? 65 c to +150 c junction temperature: +150 c lead temperature (soldering 4 sec): +260 c esd rating (hbm): 6.0 kv esd rating (mm): 400 v (1) absolute maximum ratings are those parameter values beyond which the life and operation of the device cannot be ensured. the stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. the table of ? electrical characteristics ? specifies acceptable device operating conditions. (2) it is anticipated that this device will not be offered in a military qualified version. if military/aerospace specified devices are required, please contact the texas instruments sales office / distributors for availability and specifications. recommended operating conditions symbol parameter conditions reference min typ max units v ddio cmos i/o supply voltage v ddio ? v ssio 3.150 3.300 3.450 v v ddsd sdi supply voltage v ddsi ? v sssi v ddd digital logic supply voltage v ddd ? v ssd 2.375 2.500 2.625 v v ddpll pll supply voltage v ddpll ? v sspll operating free air t a 0 +70 c temperature copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com required input conditions (1) (2) symbol parameter conditions reference min typ max units v in input voltage range v ssio v ddio v all lvcmos inputs t r , t f rise time, fall time 10% ? 90% 1.0 1.5 3.0 ns smpte 259m, level c 270 smpte 259m, level d 360 br sdi serial input data rate smpte 344m sdi, sdi 540 m bps smpte 292m 1,483 smpte 292m 1,485 v sssi v ddsi v cm(sdi) common mode voltage v in = 125 mv p-p v +1.0v ? 0.05v v in(sdi) sdi serial input voltage, 125 800 880 mv p-p single-ended v in(sdi) sdi serial input voltage, sdi, sdi 125 800 880 mv p-p differential 20% ? 80%, smpte 259m 0.4 1.0 1.5 ns data rates t r , t f rise time, fall time 20% ? 80%, smpte 292m 270 ps data rates ancillary / control data clock f aclk v clk mhz frequency dc aclk duty cycle, ancillary clock a clk 45 50 55 % ancillary / control clock and t r , t f 10% ? 90% 1.0 1.5 3.0 ns data rise time, fall time setup time, ad n to a clk or t s 3.0 1.5 ns io n to a clk rising edge control data input or io n , ad n , a clk i/o bus input timing diagram hold time, rising edge a clk t h 3.0 1.5 ns to ad n or a clk to io n bias supply reference r ref tolerance 1% 4.75k resistor f ext clk external clock frequency ext clk ? 100 +100 27.0 mhz ppm ppm f xtal crystal frequency see figure 7 xtalo, xtali (1) required input conditions are the electrical signal conditions or component values which shall be supplied by the circuit in which this device is used in order for it to produce the specified dc and ac electrical output characteristics. (2) functional and certain other parametric tests utilize a lmh0030 as the input source to the sdi inputs of the LMH0031. the lmh0030 is dc coupled to the inputs of the LMH0031. typical v in = 800 mv, v cm = 2.9 v. 6 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified (1) (2) . symbol parameter conditions reference min typ max units v ih input voltage high level 2.0 v ddio v v il input voltage low level v ssio 0.8 all lvcmos inputs i ih input current high level v ih = v ddio (3) +85 +150 a i il input current low level v il = v ssio ? 1 ? 20 v oh output voltage high level i oh = ? 2 ma 2.4 2.7 v ddio v ssio v ssio v ol output voltage low level i ol = +2 ma v ssio +0.3 +0.5v all lvcmos v v ddio outputs v ohv minimum dynamic v oh i oh = ? 2 ma (4) ? 0.5 v ssio v olp maximum dynamic v ol i ol = +2 ma (4) +0.4 v sdi serial data input voltage 125 800 880 mv p-p i sdi serial data input current sdi, sdi 1 10 a v th input thereshold over vcm range < 100 mv i bb bias supply output current r bb = 8.66k ? 1% ? 220 ? 188 a i ref reference output current r ref = 4.75k ? 1% ? 290 ? 262 270m bps data rate 38.0 45.0 power supply current, 3.3v i dd (3.3v) v ddio , v ddsi ma supply, total 1,485m bps data rate 47.0 50.0 270m bps data rate 80 120 power supply current, 2.5v i dd (2.5v) v ddd , v ddpll ma supply, total 1,485m bps data rate 220 340 (1) current flow into device pins is defined as positive. current flow out of device pins is defined as negative. all voltages are referenced to v ssio = v ssd = v sssi = 0v. (2) typical values are stated for v ddio = v ddsi = +3.3v, v ddd = v ddpll = +2.5v and t a = +25 c. (3) i ih includes static current required by input pull-down devices. (4) v ohv and v olp are measured with respect to reference ground. v olp is the peak output low voltage or ground bounce that may occur under dynamic simultaneous output switching conditions. v ohv is the lowest output high voltage or output droop that may occur under dynamic simultaneous output switching conditions. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com ac electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified (1) . symbol parameter conditions reference min typ max units serial video data inputs smpte 259m, level c 270 smpte 259m, level d 360 br sdi serial input data rate smpte 344m 540 m bps smpte 292m 1,483 sdi, sdi smpte 292m 1,485 20% ? 80%, smpte 259m 0.4 1.0 1.5 ns data rates t r , t f rise time, fall time 20% ? 80%, smpte 292m 270 ps data rates parallel video data outputs smpte 259m, 270m bps 27.0 smpte 267m, 360m bps 36.0 video output clock f vclk smpte 344m, 540m bps v clk 54.0 mhz frequency smpte 292m, 1,483m bps 74.176 smpte 292m, 1,485m bps 74.25 propagation delay, video v clk to dv n t pd 50% ? 50% 0.5 2.0 ns clock to video data valid timing diagram dc v duty cycle, video clock v clk 50 5 % 27mhz 2.0 36mhz 1.4 video data output clock t jit v clk ns p-p jitter 54mhz 1.0 74.25mhz 0.5 parallel ancillary / control data inputs, multi-function parallel bus inputs ancillary / control data clock f aclk v clk mhz frequency a clk duty cycle, ancillary data dc a anc data clock (2) 45 50 55 % clock t r , t f output rise time, fall time 10% ? 90% 1.0 1.5 3.0 setup time, ad n to a clk or t s io n , ad n , a clk 3.0 1.5 io n to a clk rising edge ns control data input or i/o bus timing diagram input hold time, rising edge a clk t h 3.0 1.5 to ad n or a clk to io n parallel ancillary / control data outputs propagation delay, clock to t pd 8.5 control data a clk to ad n 50% ? 50% ns timing diagram propagation delay, clock to t pd 11.5 ancillary data multi-function parallel i/o bus io0 ? io7 t r , t f rise time, fall time 10% ? 90% 1.0 1.5 3.0 ns timing diagram pll/cdr, format detect sd rates (3) 0.32 1.0 t lock lock detect time hd rates (3) 0.26 1.0 ms t format format detect time all rates 20 (1) typical values are stated for v ddio = v ddsi = +3.3v, v ddd = v ddpll = +2.5v and t a = +25 c. (2) when used to clock control data into or from the LMH0031, the duty cycle restriction does not apply. (3) measured from rising-edge of first sdi cycle until lock detect bit goes high (true). lock time includes cdr phase acquisition time plus pll lock time. 8 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 test loads copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: LMH0031 hi-z test eqpt. t 5k : (attenuation 0db) c l cmos outputs v ddio i ol i oh s 2 s 1 c l including probe and jig capacitance, 3pf max. s 1 - open, s 2 - closed for v oh measurement s 1 - closed, s 2 - open for v ol measurement
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com test circuit 10 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031 1.0 p f 1.0 p f 82.5 : 82.5 : +3.3 vdc +2.5 vdc 0 vdc 23 29 37 sdi v ddsi v ddio LMH0031 53 58 55 56 51 v ssio v ssd v ddd r bb sdi v ddpll v sssi 2.5v supply 3.3v supply 2.5v supply 3.3v supply output loads omitted for clarity. v sspll 52 12, 33, 62 21 22 24 25 20, 47, 59 27 28 6, 32, 39 dv0 dv1 dv2 dv3 dv4 dv5 dv6 dv7 dv8 dv9 vclk reset dv10 dv11 dv12 dv13 dv14 dv15 dv16 dv17 dv18 dv19 64 63 50 49 rd / wr anc / ctrl hd chroma, sd luma & chroma hd luma 4.7 p f 16v 0.1 p f (x2) (x2) 44 42 41 40 54 38 36 35 34 30 31 43 4.7 p f 16v 0.1 p f (x4) (x4) 10 13 14 15 18 19 16 11 98 7 5 43 1 2 46 45 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 aclk io1 io0 io2 io3 io4 io5 io6 io7 17 60 61 xtali/ext clk xtalo 825 : 825 : 8.66k 1 nf sdi sdi 57 26, 48 27 mhz clk. i/p 4.75k r ref multi- function i/o bus ancilliary/ control bus
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 timing diagram device operation introduction the LMH0031 smpte 292m/259m digital video deserializer/decoder is used in digital video signal origination and destination equipment: cameras, video tape recorders, telecines, editors, standards converters, video test and other equipment. it decodes and converts serial sdtv or hdtv component digital video signals into parallel format. the LMH0031 decoder/deserializer processes serial digital video (sdv) signals conforming to smpte 259m, smpte 344m (proposed) or smpte 292m and operates at serial data rates of 270 mbps, 360 mbps, 540 mbps, 1.483 gbps and 1.485 gbps. corresponding parallel output data rates are 27.0 mhz, 36.0 mhz, 54.0 mhz, 74.176mhz and 74.25 mhz. the LMH0031 accepts ecl or lvds serial data input signals. outputs signals are compatible with lvcmos logic devices. note in the following explanations, these logical equivalences are observed: on enabled set true logic_1 and off disabled reset false logic_0. video data path the serial data inputs (sdi) accept serial video data at smpte 259m standard definition, smpte 344m (proposed) or smpte 292m high-definition data rates. these inputs accept standard ecl or lvds signal levels and may be used single-ended or differentially. inputs may be dc or ac coupled, as required, to devices and circuits supplying the data. recommended operating conditions and all input dc and ac voltage and current specifications shall be observed when designing the input coupling circuits. for convenience, a reference bias source, pin name r ref , sets the reference current available from the input bias source, pin name r bb . the recommended nominal value of r ref is 4.75k ? , 1%. r bb is provided so that the sdi inputs may be supplied dc bias voltage via external resistors when the inputs are ac-coupled. the bias source should be loaded with a resistance to the v ss supply. the source current available at r bb is 200 a. figure 2 shows a typical input biasing scheme using r bb and r ref . copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: LMH0031 t s t h vclk (aclk) ad[9:0] input data 50% 90% 10% 90% 10% 90% 10% t r , t f t r , t f dv[19:0] output data t pd ad[9:0] output data t pd
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com figure 2. optional input biasing scheme the smpte descrambler receives nrzi serial data, converts it to nrz, then decodes it to either 10-bit standard definition or 20-bit high definition parallel video data using the reverse polynomial x 9 + x 4 + 1 as specified in the respective standard: smpte 259m, smpte 344m (proposed) or smpte 292m. the data reception bit order is lsb-first. all data processing is done at the parallel rate. the LMH0031 incorporates circuitry that implements a method for handling data that has been subjected to lsb dithering . when so enabled, data from the de-scrambler is routed for de-dithering. the de-dither enable bit in the video info 0 control register enables this function. de-dithering of data present in the vertical blanking interval can be selectively enabled by use of the v de-dither enable bit in the video info 0 control register. the initial condition of de-dither enable and v de-dither enable is off. the descrambler supplies signals to the trs character detector which identifies the presence of the valid video data. the trs character detector processes the timing reference signals which control raster framing. trs (sync) characters are detected and the video is aligned on word boundaries. data is re-synchronized with the parallel word-rate clock. interraction and operation of the character alignment control signals and indicators framing mode , framing enable and nsp (new sync position) is described later in this datasheet. the LMH0031 implements trs character lsb-clipping as prescribed in itu-r bt.601. lsb-clipping causes all trs characters with a value between 000h and 003h to be forced to 000h and all trs characters with a value between 3fch and 3ffh to be forced to 3ffh. clipping is done after descrambling and de-dithering. 12 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031 82.5 : 1 p f 1 nf 4.75 k : 8.66 k : sdi r bb r ref sdi LMH0031 825 : 825 : 82.5 : 1 p f
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 once the pll attains lock, the video format detector processes the received data to determine the raster characteristics (video data format) and configure the LMH0031 to handle it. this assures that the parallel output data will be properly formatted, that the correct data rate is selected and that ancillary data and crc/edh data are correctly detected and checked. supported parallel data formats or sub-formats may belong to any one of several component standards: smpte 125m, smpte 267m, smpte 260m, 274m, 295m or 296m. refer to table 4 for the supported formats. (see also the application information section for handling of other raster formats or format extensions developed after this device was designed). the detected video standard information is passed to the device control system and saved in the control registers from whence it may be read by the user. the LMH0031 may be configured to operate in a single video format by loading the appropriate format set[4:0] control data into the format 0 control register. also, the LMH0031 may be configured to handle only the standard-definition data formats by setting the sd only bit or only the high-definition data formats by setting the hd only bit in the format 0 control register. when both bits are reset, the default condition, the part automatically detects the data rate and range. aligned and de-processed parallel data passes into a variable-depth video fifo prior to output. video fifo depth from 0 to 4 registers is set by a 3-bit word written into the video fifo depth[2:0] bits in the anc 0 control register. the video fifo permits adjustment of the parallel video data output timing or delay at a parallel word rate. the occurence of corresponding trs indicator bits, eav, sav and nsp, in the control register corresponds to the input register position of the fifo. this positioning permits a look-ahead function in which the alignment status of the video data can be determined up to four parallel clock periods prior to the appearance of that data at the parallel data output. the parallel video data is output on dv[19:0] . the 20-bit parallel video data is organized so that for hdtv data, the upper-order 10 bits dv[19:10] are luminance (luma) information and the lower 10 bits dv[9:0] are colour difference (chroma) information. sdtv data use the lower-order 10-bits dv[9:0] for both luma and chroma information. (the sdtv parallel data is also duplicated on dv[19:10] ). v clk is the parallel output word rate clock signal. the frequency of v clk is appropriate to either the hd or sd data being processed. data is valid between the falling edges of a v clk cycle. data may be clocked into external devices on the rising-edge of v clk . the dv[19:0] and v clk signals are lvcmos-compatible. ancillary/control data path the 10-bit ancillary and control data portad[9:0] serves two functions in the LMH0031. ancillary data from the ancillary data fifo is output from this port after its recovery from the video data stream. the utilization and flow of ancillary data from the device is managed by a system of control bits, masks and ids stored in the control data registers. this port also provides read/write access to contents of the configuration and control registers. the signals rd/ wr , anc/ ctrl and a clk control data flow through the port. control data functions control data is input to and output from the LMH0031 using the lower-order 8 bits ad[7:0] of the ancillary/control data port. this control data initializes, monitors and controls operation of the LMH0031. the upper two bits ad[9:8] of the port function as handshaking signals with the device accessing the port. when either a control register read or write address is being written to the port, ad[9:8] must be driven as 00b (0xxh, where xx are ad[7:0]). when control data is being written to the port, ad[9:8] must be driven as 11b (3xxh, where xx are ad[7:0]). when control data is being read from the port, the LMH0031 will output ad[9:8] as 10b (2xxh, where xx are output data ad[7:0]) and may be ignored by the monitoring system. note after either a manual or power-on reset, a clk must be toggled three (3) times to complete initiallization of the ancillary and control data port . the sequence of clock and control signals for reading control data from the ancillary/control data port is shown in figure 3 . control data read mode is invoked by making the anc/ ctrl input low and the rd/ wr input high. the 8-bit address of the control register set to be accessed is input to the port on bits ad[7:0] . to identify the data as an address, ad[9:8] must be driven as 00b. the complete address word will be 0xxh, where 0 is ad[9:8] and xx are ad[7:0]. the address is captured on the rising edge of a clk . when control data is being read from the port, the LMH0031 will output ad[9:8] as 10b (2xxh, where xx are output data ad[7:0]) and may be ignored by the monitoring system. data being output from the selected register is driven by the port copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com immediately following the rising edge of a clk or when the address signal is removed. for optimum system timing, the signals driving the address to the port should be removed immediately after the address is clocked into the port and before or simultaneously with the falling edge of a clk at the end of that address cycle. output data remains stable until the next rising edge of a clk and may be written into external devices at any time after the removal of the address signal. this second clock resets the port from drive to receive and readies the port for another access cycle. example: read the full-field flags via the ad port. 1. set anc/ ctrl to a logic-low. 2. set rd/ wr to a logic-high. 3. present 001h to ad[9:0] as the register address. 4. toggle a clk . 5. release the bus driving the ad port. 6. read the data present on the ad port. the full-field flags are bits ad[4:0]. 7. toggle a clk to release the ad port. figure 4 shows the sequence of clock and control signals for writing control data to the ancillary/control data port. the control data write mode is similar to the read mode. control data write mode is invoked by making the anc/ ctrl input low and the rd/ wr input low. the 8-bit address of the control register set to be accessed is input to the port on bits ad[7:0] . when a control register write address is being written to the port, ad[9:8] must be driven as 00b (0xxh, where xx are ad[7:0]). the address is captured on the rising edge of a clk . the address data is removed on the falling edge of a clk . next, the control data is presented to the port bits ad[7:0] and written into the selected register on the next rising edge of a clk . when control data is being written to the port, ad[9:8] must be driven as 11b (3xxh, where xx are ad[7:0]). control data written into the registers may be read out non-destructively in most cases. example: setup (without enabling) the tpg mode via the ad port using the 1125 line, 30 frame, 74.25mhz, interlaced component (smpte 274m) colour bars as test pattern. the tpg may be enabled after setup using the multi-function i/o port or by the control registers. 1. set anc/ ctrl to a logic-low. 2. set rd/ wr to a logic-low. 3. present 00dh to ad[9:0] as the test 0 register address. 4. toggle a clk . 5. present 327h to ad[9:0] as the register data. 6. toggle a clk . figure 3. control data read timing (2 read and 1 write cycle shown) 14 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031 rd / wr anc / ctrl addr data data addr addr data ad[7:0] write external bus must release internal bus will release aclk read read ad[9:8] ad[9] ad[8] driven rec'd driven rec'd driven driven ad[9] ad[8] ad[8] ad[9] ad[8] ad[9:8]
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 figure 4. control data write timing ancillary data functions the LMH0031 can recover ancillary data from the serial data stream. this ancillary data and related control characters are defined in the relevant smpte standards and may reside in the horizontal and vertical blanking intervals. the data can consist of different types of message packets including audio data. the serial ancillary data space must be formatted according to smpte 291m. the LMH0031 supports ancillary data in the chrominance channel (c ? r/c ? b) only for high-definition operation. ancillary data for standard definition follows the requirements of smpte 125m. the ancillary data fifo is sized to handle a maximum length anc data type 1 or type 2 packet without the anc flag, 259 words. defined in smpte 291m, the packet consists of the ancillary data flag, a 3-word data id and data count, 255 8- or 10-bit user data words and a checksum. the design of the LMH0031 ancillary data fifo also allows storage of up to 8 shorter length messages with total length not exceeding 259 words including all id information. ancillary data is copied from the data stream into the ancillary data fifo . the parallel ancillary data will still be present in the parallel chroma output dv[9:0] . ancillary flag information is not extracted into the fifo. copying of anc data from the video data into the fifo is controlled by the anc mask and anc id bits in the control registers. a system of flags, anc fifo empty , anc fifo 90% full , anc fifo full and anc fifo overrun are used to monitor fifo status. the details and functions of these and other control words are explained later in this datasheet. figure 5 shows the relationship of clock, data and control signals for reading ancillary data from the port ad[9:0] . in ancillary data read mode, 10-bit ancillary data is routed from the ancillary data fifo and read from the port ad[9:0] at a rate determined by a clk . ancillary data read (output) mode is invoked by making the anc/ ctrl input high and the rd/ wr input high. ancillary data is clocked from the fifo on the l-h transition of a clk . data may be read from the port on rising edges of a clk , after the specified propagation delay, until the fifo is emptied. data may only be read from the port when in the ancillary data mode. ancillary data cannot be written to the port. to conserve power when the ancillary data function is not being used, the internal ancillary data fifo clock is disabled. this clock must be enabled before ancillary data may be replicated into the fifo for output. this internal fifo clock is controlled by fifo clock enable , bit-6 of the anc 5 register (address 17h). the default condition of fifo clock enable is off. after enabling the internal fifo clock by turning this bit on, a clk must be toggled three (3) times to propagate the enable to the clock tree. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com figure 5. ancillary data read timing multi-function i/o port the multi-function i/o port can be configured to provide immediate access to many control and indicator functions that are stored within the LMH0031 ? s configuration and control registers. the individual pins comprising this port are assigned as input or output for selected functions stored in the control data registers. the multi-function i/o port is configured by way of an 8x6-bit register bank consisting of registers i/o pin 0 config through i/o pin 7 config . the contents of these registers determine whether the port bits function as inputs or outputs and to which control function or indicator each port bit is assigned. port bits may be assigned to access different functions and indicators or any or all port bits may be assigned to access the same function or indicator (output mode only). the same indicator or function should not be assigned to more than one port bit as an input. controls and indicators that are accessible by the port and their corresponding selection addresses are given in the i/o pin configuration register addresses, table 6 . table 2 gives the control register bit assignments. data resulting from device operation will be sent to the selected i/o port bit. this same data is also stored in the configuration and control registers. mapping the control and indicator functions in this manner means that device operation will be immediately reflected at the i/o port pins thereby ensuring more reliable real-time operation of the device within and by the host system. when a multifunction i/o port bit is used as input to a control register bit, data must be presented to the i/o port bit and clocked into the register bit using a clk as shown in figure 6 . port timing for bit write operations is the same as for the anc/ ctrl port operation. figure 6. i/o port data write timing example: program multi-function i/o port bit-0 as the crc luma error bit output. 1. set anc/ ctrl to a logic-low. 2. set rd/ wr to a logic-low. 3. present 00fh to ad[9:0] as the i/o pin 0 config register address. 4. toggle a clk . 5. present 310h to ad[9:0] as the register data. 6. toggle a clk . 16 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031 aclk rd/wr anc/ctrl ad[9:0] read data data data data data data data aclk multifunction i/o port bit
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 edh/crc system the LMH0031 has edh and crc character generation and checking circuitry. the edh system functions as described in smpte recommended practice rp-165. the crc system functions as specified in smpte 292m. the edh/crc polynomial generators/checkers accept parallel data from the de-serializing system and generate the edh and crc check words for comparison with those received in the data. the edh enable bit in the control register enables the edh generation and checking system. incoming sdtv data is checked for errors and the edh flags are updated automatically. edh errors are reported in the edh0, edh1, and edh2 register sets of the configuration and control registers. updated or new edh check words and flags may be generated and inserted in the data. edh check words are generated using the polynomial x 16 + x 12 + x 6 + 1 per smpte rp165. generation and automatic insertion of new or corrected edh check words is controlled by edh force and edh enable bits in the control registers. edh check words and status flags are inserted in the parallel data at the correct positions in the ancillary data space and formatted per smpte 291m. after a reset, the initial state of all edh and crc check characters is 00h. the smpte 292m high definition video standard employs crc (cyclic redundancy check codes) error checking instead of edh. the crc consists of two 18-bit words generated using the polynomial x 18 + x 5 + x 4 + 1 per smpte 292m. one crc is used for luminance and one for chrominance data. the crcs appear in the data stream following the eav and line number characters. the crcs are checked and errors are reported in the edh0, edh1, and edh2 register sets of the configuration and control registers. phase-locked loop / clock-data recovery system the phase-locked loop and clock-data recovery (pll/cdr) system generates all internal timing and data rate clocks for the LMH0031. the pll/cdr system consists of five main functional blocks: 1) the input buffer which receives the incoming data, 2) input data samplers which oversample the data coming from the input buffer, 3) a pll (vco, divider chain, phase-frequency detector and internal loop filter) which generates sampling and other system clocks, 4) a digital cdr system to recover the oversampled serial input data from the samplers and the digital system control and 5) a rate detect controller which sequences the pll to find the data rate. using an oversampling technique, the timing information encoded in the serial data is extracted and used to synchronize the recovered clock and data. the parallel data rate and other clock signals are derived from the regenerated serial clock. the parallel data rate clock is 1/10th of the serial data rate clock for standard definition or 1/20th of the serial data clock frequency for high definition. the data interface between the cdr and the digital processing block uses 10-bit data plus the required clocks. the pll is held in coarse frequency lock by an external 27mhz clock signal, ext clk , or by an external 27mhz crystal and internal oscillator. upon power-on, ext clk is the default reference. the internal oscillator and an external crystal may be used as the reference by setting the oscen bit in the cdr register . the reference clock reduces lock latency and enhances format and auto-rate detection robustness. pll acquisition, data phase alignment and format detection time is 20ms or less at 1.485mbps. the vco has separate v ddpll and v sspll power supply feeds, pins 51 and 52, which may be supplied power via an external low-pass filter, if desired. figure 7. crystal and load circuit a 27mhz crystal and load circuit may be used to provide the reference clock. a fundamental mode crystal with the following parameters is used: frequency 27mhz, frequency tolerance 30ppm, load capacitance 18pf, maximum drive level 100 w, equivalent series resistance < 50 , operating temperature range 0 c to 70 c. refer to figure 7 for a typical load circuit and connection information. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: LMH0031 27mhz 33pf 33pf pin 60 pin 61
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com the LMH0031 indicates that the pll is locked to the incoming data rate and that the cdr has acquired a phase of the serial data by setting the lock detect bit in the video info 0 control register. indication of the standard being processed is retained in the format[4:0] bits in the format 1 control data register. format data from this register can be programmed for output on the multi-function i/o port. the power-on default assigns lock detect as i/o port bit 4. power supplies, power-on-reset and reset input the LMH0031 requires two power supplies, 2.5v for the core logic functions and 3.3v for the i/o functions. the supplies must be applied to the device in proper sequence. the 3.3v supply must be applied prior to or coincident with the 2.5v supply. application of the 2.5v supply must not precede the 3.3v supply. it is recommended that the 3.3v supply be configured or designed so as to control application of the 2.5v supply in order to satisfy this sequencing requirement. the LMH0031 has an automatic, power-on-reset circuit. reset initializes the device and clears trs detection circuitry, all latches, registers, counters and polynomial generators/checkers and resets the edh/crc characters to 00h. an active-high-true, manual reset input is available at pin 49. the reset input has an internal pull-down device and may be considered inactive when unconnected. important: when power is first applied to the device or following a reset, the ancillary and control data port must be initialized to receive data. this is done by toggling a clk three times. test pattern generator (tpg) and built-in self-test (bist) the LMH0031 includes an on-board, parallel video test pattern generator (tpg) . four test pattern types are available in both hd and sd formats, ntsc and pal standards, and 4x3 and 16x9 raster sizes. the test patterns are: flat-field black, pll pathological, equalizer (eq) pathological and a 75%, 8-colour vertical bar pattern. the pathologicals follow recommendations contained in smpte rp 178-1996 regarding the test data used. the colour bar pattern has optional bandwidth limiting coding in the chroma and luma data transitions between bars. the vpg filter enable bit in the video info 0 control register enables the colour bar filter function. the test pattern data is available at the video data outputs, dv[19:0] with a corresponding parallel rate clock, vclk , appropriate to the particular standard and format selected. the tpg also functions as a built-in self-test (bist) which can be used to verify device functionality. the bist function performs a comprehensive go/no-go test of the device. the test may be run using any of the hd colour bar patterns or one of two sd patterns, either the 270 mb/s ntsc colour bar or the pal pll pathological, as the test data pattern. data is input from the digital processing block, processed through the device and tested for errors using either the edh system for sd or the crc system for hd. clock signals from the cdr block supply timing for the test data. the cdr must be supplied a 27mhz reference clock via the xtali/ext clk input (or using the internal oscillator and crystal) during the tpg or bist function. a go/no-go indication is logged in the pass/ fail bit of the test 0 control register set. this bit may be assigned as an output on the multifunction i/o port. tpg and bist operation is initiated by loading the code for the desired test pattern into the test pattern select[5:0] bits and by setting the tpg enable bit of the test 0 register. note that when attempting to use the tpg or bist immediately after the device has been reset or powered on, the tpg defaults to the 270mbps sd rate. the device must be configured for the desired test pattern by loading the appropriate code in to the test 0 register. if hd operation is desired, selection of the desired hd test pattern is sufficient to enable the device to configure itself to run at the correct rate and generate valid data. table 5 gives the available test patterns and codes. the pass/ fail bit in the control register gives the device test status indication. if no errors have been detected, this bit will be set to logic-1 approximately 2 field intervals after tpg enable is set. if errors have been detected in the internal circuitry of the LMH0031, pass/ fail will remain reset to a logic-0. tpg or bist operation is stopped by resetting the tpg enable bit. parallel output data is present at the dv[19:0] outputs during tpg or bist operation. example: enable the tpg mode to use the ntsc 270mbps colour bars as the bist and tpg pattern. enable tpg operation using the i/o port. 1. set anc/ ctrl to a logic-low. 2. set rd/ wr to a logic-low. 3. present 00dh to ad[9:0] as the test 0 register address. 18 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 4. toggle a clk . 5. present 343h to ad[9:0] as the register data (525 line, 30 frame, 27mhz, ntsc 4x3, colour bars (smpte 125m)). 6. toggle a clk . 7. the pass/ fail indicator, test 0 register, bit 7, should be read for the result of the test. alternatively, this bit may be mapped to a convenient bit of the multi-function i/o bus. the test pattern data and clock is available at the dv[19:0] and v clk outputs. configuration and control registers the configuration and control registers store data which determines the operational modes of the LMH0031 or which result from its operation. many of these registers may be assigned as external i/o functions which are then available on the multi-function i/o bus. these functions are summarized in table 1 and detailed in table 2 . the power-on default condition for the multi-function i/o port is indicated in table 1 and detailed in table 6 . table 1. configuration and control data register summary (1) available on register function bits read or write initial condition notes i/o bus edh and crc operations crc error (sd/hd) 1 r reset output see (2) i/o 5 crc error luma 1 r reset output crc error chroma 1 r reset output crc replace 1 r/w off no see (3) full-field flags 5 r reset no active picture flags 5 r reset no anc flags 5 r reset no edh force 1 r/w off input edh enable 1 r/w on input f/f flag error 1 r reset output a/p flag error 1 r reset output anc flag error 1 r reset output ancillary data operations anc checksum force 1 r/w off input anc checksum error 1 r reset output anc fifo empty 1 r set output see (2) i/o 6 anc fifo 90% full 1 r reset output anc fifo full 1 r reset output anc fifo overrun 1 r reset output anc id 16 r/w 0000h no anc mask 16 r/w ffffh no msg track 1 r/w off no msg flush static 1 r/w off no fifo flush static 1 r/w off no full msg available 1 r off output short msg detect 1 r off output fifo clock enable 1 r/w off no fifo extract enable 1 r/w off input video fifo operation video fifo depth 3 r/w 000b no (1) on = set = logic-1, off = reset = logic-0 (positive logic). (2) connected to multifunction i/o port at power-on. (3) special or restricted functionality. refer to text for details. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com table 1. configuration and control data register summary (1) (continued) available on register function bits read or write initial condition notes i/o bus video format operations format set 5 r/w 00000b no sd only 1 r/w off no hd only 1 r/w off no format 5 r output format [4] (2) i/o 3 h 1 r output see (2) i/o 2 v 1 r output see (2) i/o 1 f 1 r output see (2) i/o 0 framing mode 1 r/w on no framing enable 1 r/w on input new sync position (nsp) 1 r output sav 1 r output eav 1 r output see (2) i/o 7 de-scramble enable 1 r/w on no nrzi enable 1 r/w on no lsb clipping enable 1 r/w on no sync detect enable 1 r/w on no de-dither enable 1 r/w off input vert. de-dither enable 1 r/w off input lock detect 1 r output see (4) i/o 4 unscrambled 1 r/w off no see (5) video data out tpg and bist operations test pattern select 6 r/w 000000b input 525/27 mhz/black tpg enable 1 r/w off input pass/fail 1 r output vpg filter enable 1 r/w off input reference clock operations reference clock 2 r/w 00b no ext clk enabled external vclk 1 r/w off no see (5) multifunction i/o bus operations i/o bus pin config. 48 r/w see table 6 no (4) connected to multifunction i/o port at power-on. (5) special or restricted functionality. refer to text for details. table 2. control register bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 edh 0 (register address 01h) crc error edh force edh enable f/f ues f/f ida f/f idh f/f eda f/f edh edh 1 (register address 02h) crc crc error crc error a/p ues a/p ida a/p idh a/p eda a/p edh replace luma chroma edh 2 (register address 03h) f/f flag a/p flag anc flag anc ues anc ida anc idh anc eda anc edh error error error anc 0 (register address 04h) video video video anc fifo anc fifo anc fifo anc check- anc check- fifo-depth(2) fifo-depth(1) fifo-depth(0) overrun empty full sum error sum force 20 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 table 2. control register bit assignments (continued) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 anc 1 (register address 05h) anc id(7) anc id(6) anc id(5) anc id(4) anc id(3) anc id(2) anc id(1) anc id(0) anc 2 (register address 06h) anc id(15) anc id(14) anc id(13) anc id(12) anc id(11) anc id(10) anc id(9) anc id(8) anc 3 (register address 07h) anc mask(7) anc mask(6) anc mask(5) anc mask(4) anc mask(3) anc mask(2) anc mask(1) anc mask(0) anc 4 (register address 08h) anc anc anc anc mask(15) anc mask(14) anc mask(13) anc mask(9) anc mask(8) mask(12) mask(11) mask(10) anc 5 (register address 17h) fifo extract fifo clock full msg fifo flush msg flush reserved reserved msg track enable enable available static static anc 6 (register address 18h) anc fifo short msg anc parity reserved reserved reserved reserved vanc 90% full detect mask format 0 (register address 0bh) framing format format format format format sd only hd only mode set(4) set(3) set(2) set(1) set(0) format 1 (register address 0ch) f v h format(4) format(3) format(2) format(1) format(0) test 0 (register address 0dh) test test test test test test pattern pass/fail tpg enable pattern pattern pattern pattern pattern select(5) select(4) select(3) select(2) select(1) select(0) video info 0 (register address 0eh) vert. de- de-dither vpg filter lock framing dither eav sav nsp enable enable detect enable enable video control 0 (register address 55h) external sync detect lsb clip de-scramble reserved reserved nrzi enable reserved v clk enable enable enable reference clock (register address 67h) reserved reserved reserved reserved reserved int_osc en clk en reserved multi-function i/o bus pin configuration i/o pin 0 config (register address 0fh) reserved reserved pin 0 sel[5] pin 0 sel[4] pin 0 sel[3] pin 0 sel[2] pin 0 sel[1] pin 0 sel[0] i/o pin 1 config (register address 10h) reserved reserved pin 1 sel[5] pin 1 sel[4] pin 1 sel[3] pin 1 sel[2] pin 1 sel[1] pin 1 sel[0] i/o pin 2 config (register address 11h) reserved reserved pin 2 sel[5] pin 2 sel[4] pin 2 sel[3] pin 2 sel[2] pin 2 sel[1] pin 2 sel[0] i/o pin 3 config (register address 12h) reserved reserved pin 3 sel[5] pin 3 sel[4] pin 3 sel[3] pin 3 sel[2] pin 3 sel[1] pin 3 sel[0] i/o pin 4 config (register address 13h) reserved reserved pin 4 sel[5] pin 4 sel[4] pin 4 sel[3] pin 4 sel[2] pin 4 sel[1] pin 4 sel[0] i/p pin 5 config (register address 14h) reserved reserved pin 5 sel[5] pin 5 sel[4] pin 5 sel[3] pin 5 sel[2] pin 5 sel[1] pin 5 sel[0] i/o pin 6 config (register address 15h) reserved reserved pin 6 sel[5] pin 6 sel[4] pin 6 sel[3] pin 6 sel[2] pin 6 sel[1] pin 6 sel[0] i/o pin 7 config (register address 16h) reserved reserved pin 7 sel[5] pin 7 sel[4] pin 7 sel[3] pin 7 sel[2] pin 7 sel[1] pin 7 sel[0] copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com table 3. control register addresses address register name hexadecimal edh 0 01 edh 1 02 edh 2 03 anc 0 04 anc 1 05 anc 2 06 anc 3 07 anc 4 08 anc 5 17 anc 6 18 format 0 0b format 1 0c test 0 0d video info 0 0e i/o pin 0 config 0f i/o pin 1 config 10 i/o pin 2 config 11 i/o pin 3 config 12 i/o pin 4 config 13 i/o pin 5 config 14 i/o pin 6 config 15 i/o pin 7 config 16 video control 0 55 video control 1 56 reference clock 67 edh 0 (register 01h) the edh full-field flags f/f ues , f/f ida , f/f idh , f/f eda and f/f edh are defined in smpte rp 165. the flags are updated automatically when the edh function is enabled and data is being received. the edh enable bit, when set, enables operation of the edh generator function during sd operation. the default condition of this bit is set (on). the edh force bit, when set, causes updated edh packets to be inserted in the parallel output data regardless of the previous condition of edh checkwords and flags in the input serial data. this function may be used in situations where video content has been edited thus making the previous edh information invalid. the default condition of this bit is reset (off). the crc error bit indicates that errors in either the edh checksums (sd) or crc checkwords (hd) were detected in the serial input data. this bit is a combined function which indicates the presence of either edh errors during sd operation or crc errors during hd operation. edh 1 (register 02h) the edh active picture flags a/p ues , a/p ida , a/p idh , a/p eda and a/p edh are defined in smpte rp 165. the flags are updated automatically when the edh function is enabled and data is being received. specific types of crc errors in incoming hd serial data are reported in the crc error luma and crc error chroma bits. the crc replace bit, when set, causes the crcs in the incoming data to be replaced with crcs calculated by the LMH0031. the bit is normally reset (off). 22 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 edh 2 (register 03h) the edh ancillary data flags anc ues , anc ida , anc idh , anc eda and anc edh are defined in smpte rp 165. the flags are updated automatically when the edh function is enabled and data is being received. the status of edh flag errors in incoming sd serial data are reported in the ffflagerror , apflagerror and ancflagerror bits. each of these bits is the logical-or of the corresponding edh and eda flags. anc 0 (address 04h) the v fifo depth[2:0] bits control the depth of the video fifo which preceeds the parallel output data drivers. the depth can be set from 0 to 4 stages by writing the corresponding binary code into these bits. for example: to set the video fifo depth at two registers, load 11010xxxxxb into the anc 0 control register (where x represents the other functional bits of this register). note when changing some but not all bits in a register and to retain unchanged other data previously stored in the register, read the register ? s contents and logically-or this with the new data. then write the modified data back into the register. flags for anc fifo empty , anc fifo 90% full , anc fifo full and anc fifo overrun are available in the configuration and control register set. these flags can also be assigned as outputs on the multi-function i/o port. anc fifo empty when set indicates that the fifo contains no data. anc fifo 90% full indicates when the fifo is at 90% of capacity. since it is virtually impossible for the host processor to begin extracting data from the fifo after it has been flagged as full without the possibility of an overrun condition occurring, anc fifo 90% full is used as an advanced command to the host to begin extracting data from the fifo. to be used properly, anc fifo 90% full should be assigned as an output on the multi-function i/o port and monitored by the host system. otherwise, inadvertent loss of ancillary packet data could occur. anc fifo full when set indicates that the fifo registers are completely filled with data. the anc fifo overrun flag indicates that an attempt to write data into a full fifo has occurred. anc fifo overrun can be reset by reading the bit's status via the ancillary/control port. if an overrun occurrs, the status of the fifo message tracking will be invalidated. in this event, the fifo should be flushed to reset the message tracking pointers. any messages then in the fifo will be lost. the anc checksum force bit, under certain conditions, enables the overwriting of ancillary data checksums received in the data. calculation and insertion of new ancillary data checksums is controlled by the anc checksum force bit. if a checksum error is detected (calculated and received checksums do not match) and the anc checksum force bit is set, the anc checksum error bit is set and a new checksum is inserted in the ancillary data replacing the previous one. if a checksum error is detected and the anc checksum force bit is not set, the checksum mismatch is reported via the anc checksum error bit. anc checksum error is available as an output on the multifunction i/o port. anc 1 and 2 (addresses 05h and 06h) the extraction of ancillary data packets from video data into the fifo is controlled by the anc mask[15:0] and anc id[15:0] bits in the control registers. the anc id[7:0] register normally is set to a valid 8-bit code used for component ancillary data packet did identification as specified in smpte 291m-1998. similarly, anc id[15:8] normally is set to a valid 8-bit code used for component ancillary data packet sdid/dbn identification. anc 3 and 4 (addresses 07h and 08h) the anc mask[7:0] is an 8-bit word that can be used to selectively control extraction of packets with specific dids (or did ranges) into the fifo. when the anc mask[7:0] is set to ffh, packets with any did can be extracted into the fifo. when any bit or bits of the anc mask[7:0] are set to a logic-1, the corresponding bit or bits of the anc id[7:0] are a don't-care when matching dids of packets being extracted. when the anc mask[7:0] is set to 00h, the anc did of incoming packets must match exactly, bit-for-bit the anc id[7:0] set in the control register for the packets to be extracted into the fifo. the initial value of the anc mask[7:0] is ffh and the anc id[7:0] is 00h. similarly, anc mask[15:8] is an 8-bit word that can be used to selectively control extraction of packets with specific sdid/dbn (or sdid/dbn ranges) into the fifo. operation and use of these bits is the same as for anc mask[7:0] previously discussed. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com anc 5 (address 17h) the fifo extract enable bit in the control registers enables the device to extract or copy ancillary data from the video data stream and place it in the anc fifo. from there data may be output via the parallel ancillary port. data extraction is enabled when this bit is set to a logic-1. this bit can be used to delay automatic extraction and therefore the output of parallel ancillary data. fifo extract enable should be asserted during an sav or eav to avoid timing problems with ancillary data extraction. access to data in the fifo is controlled by the rd/ wr , anc/ ctrl and a clk control signals. to conserve power when the ancillary data function is not being used, the internal ancillary data fifo clock is disabled. this clock must be enabled before ancillary data may be replicated into the fifo for output. fifo clock enable , bit-6 of the anc 5 register (address 17h), when set, enables this clock to propagate to the fifo. the default condition of fifo clock enable is off. after enabling the internal fifo clock by turning this bit on, a clk must be toggled three (3) times to propagate the enable to the clock tree. a clk should remain running at all times when the anc fifo is in use. otherwise, message tracking and related functions will not operate correctly. the LMH0031 can keep track of up to 8 anc data packets in the anc fifo. incoming packet length versus available space in the fifo is also tracked. the msg track bit in the control registers, when set, enables tracking of packets in the fifo. other functions for control of packet traffic in the fifo are fifo flush stat and msg flush stat . if the user wishes to handle more than 8 messages, the msg track bit should be turned off (reset). the operation fifo flush stat will no longer work and the function full msg available will no longer be a reliable indicator that messages are available in the fifo. the user may still effectively use the fifo by monitoring the states of anc fifo empty , anc fifo full , anc fifo 90%full and anc fifo overrun . setting the fifo flush stat bit to a logic-1 flushes the fifo. fifo flush stat may not be set while the fifo is being accessed (read or write). fifo flush stat is automatically reset after this operation is complete. when msg flush stat is set to a logic-1, the oldest message packet in the fifo is flushed when data is not being written to the fifo. msg flush stat is automatically reset after this operation is complete. the full msg available bit in the control registers, when set, notifies the host system that complete packets reside in the ancillary data fifo. when this bit is not set, the messages in the fifo are incomplete or partial. this function is not affected by msg track . the full msg available function is most useful when mapped to the multifunction i/o port as an output. anc 6 (address 18h) the anc fifo 90% full flag bit indicates when the anc fifo is 90% full. this bit may be mapped to the multi-function i/o port. the purpose of this flag is to provide a signal which gives the host system time to begin reading from the fifo before it has the chance to overflow. this was done because it is virtually impossible to monitor the fifo full flag and begin extracting from the fifo before an overrun condition occurs. the short msg detect flag bit indicates when short anc messages have been detected. i.e. an anc header was detected before the last full message was recovered. this bit may be mapped to the multi-function i/o port. the anc parity mask bit when set disables parity checking for did and sdid words in the anc data packet. when reset, parity checking is enabled; and, if a parity error occurs, the packet will not be extracted. the vanc bit, when set, enables extraction of anc data present in the vertical blanking interval (both active video and horizontal blanking portions of the line). format 0 (address 0bh) the LMH0031 may be set to process a single video format by writing the appropriate data into the format 0 register. the format set[4:0] bits confine the LMH0031 to recognize and process only one of the fourteen specified type of sd or hd formats defined by a particular smpte specification. the format set[4:0] bits may not be used to confine device operation to a range of standards. the available formats and codes are detailed in table 4 . generally speaking, the format set[4:0] codes indicate or group the formats as follows: format set[4] is set for the hd data formats, reset for sd data formats. format set[3] is set for pal data formats (with the exception of the smpte 274m 24-frame progressive format), reset for ntsc data formats. format set[2:0] further sub-divide the standards as given in the table. 24 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 table 4. video raster format parameters format frame active code format spec. (1) lines active lines samples rate samples [4,3,2,1,0] 00001 sdtv, 54 rp 174 60i 525 507/487* 3432 2880 00010 sdtv, 36 smpte 267 60i 525 507/487* 2288 1920 00011 sdtv, 27 smpte 125 60i 525 507/487* 1716 1440 01001 sdtv, 54 itu-r bt 601.5 50i 625 577 3456 2880 01010 sdtv, 36 itu-r bt 601.5 50i 625 577 2304 1920 01011 sdtv, 27 itu-r bt 601.5 50i 625 577 1728 1440 10001 hdtv, 74.25 smpte 260 30i 1125 1035 2200 1920 10010 hdtv, 74.25 smpte 274 30i 1125 1080 2200 1920 10011 hdtv, 74.25 smpte 274 30p 1125 1080 2200 1920 11001 hdtv, 74.25 smpte 274 25i 1125 1080 2640 1920 11010 hdtv, 74.25 smpte 274 25p 1125 1080 2640 1920 11100 hdtv, 74.25 smpte 295 25i 1250 1080 2376 1920 11101 hdtv, 74.25 smpte 274 24p 1125 1080 2750 1920 10100 hdtv, 74.25 smpte 296 (1, 2) 60p 750 720 1650 1280 (1) spec. is ensured by design. the hd only bit when set to a logic-1 locks the LMH0031 into the high definition data range and frequency. in systems designed to handle only high definition signals, enabling hd only reduces the time required for the LMH0031 to establish frequency lock and determine the hd format being processed. the sd only bit when set to a logic-1 locks the LMH0031 into the standard definition data ranges and frequencies. in systems designed to handle only standard definition signals, enabling sd only reduces the time required for the LMH0031 to establish frequency lock and determine the format being processed. when sd only and hd only are set to logic-0, the device operates in sd/hd mode. the framing mode bit in the format 0 register and framing enable in the video info 0 register combine with framing enable to control the manner in which the LMH0031 aligns framing. when framing mode and framing enable are both reset, the LMH0031 aligns on the first valid trs character. if another trs occurs that is not on a word boundary, the nsp bit is set until the next trs that is on a word boundary occurs. when framing mode is set to a logic-1, the LMH0031 operates similarly to the clc011 when nsp is tied to fe. an alternative configuration that operates identically can be achieved with the LMH0031 by mapping nsp as an output and framing enable as an input on the multifunction i/o bus and externally connecting them. in this case framing mode should be reset to a logic-0. when framing mode is reset and framing enable is set, the LMH0031 realigns on every valid trs. the initial state of framing mode is set following a reset or at power-on. format 1 (address 0ch) the LMH0031 automatically determines the format of the incoming serial data. the result of this operation is stored in the format 1 register. the format[4:0] bits identify which of the many possible video data standards that the LMH0031 can process is being received. these format codes follow the same arrangement as for the format set[4:0] bits. these formats and codes are given in table 4 . bit format[4] when set indicates that hd data is being processed. when reset, sd data is indicated. format[3] when set indicates that pal data is being processed. when reset ntsc data is being processed. format[2:0] correspond with one of the sub-standards given in the table. note that the LMH0031 does not distinguish or log the data rate differences between hd data at 74.25mhz and 74.25mhz/1.001. the h, v, and f bits correspond to input trs data bits 6, 7 and 8, respectively. the meaning and function of this data is the same for both standard definition (smpte 125m) and high definition (smpte 292m luminance and colour difference) video data. polarity is logic-1 equals high-true. these bits are registered for the duration of the applicable field. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com test 0 register (address 0dh) the test pattern select bits determine which test pattern is output when the test pattern generator (tpg) mode or the built-in self-test (bist) mode is enabled. table 5 gives the codes corresponding to the various test patterns. all hd colour bar test patterns are inherently bist data. bist test patterns for sd are: ntsc, 27mhz, 4x3 colour bars and pal, 27mhz, 4x3 pll pathological. the tpg enable bit when set to a logic-1 enables the test pattern generator function and built-in self-test (bist). the pass/ fail bit indicates the result of the built-in self-test. this bit is a logic-1 for a pass condition. table 5. test pattern selection codes (1) test pattern select word bits > bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1=hd 1=progressive 00=black 0=interlaced 01=pll path. video raster standard 0=sd 1=pal 10=eq path. 0=ntsc 11=colour bars 1125 line, 74.25 mhz, 30 frame interlaced component (smpte 260m) ref. black 1 0 0 0 0 0 pll path. 1 0 0 0 0 1 eq path. 1 0 0 0 1 0 colour bars 1 0 0 0 1 1 1125 line, 74.25 mhz, 30 frame interlaced component (smpte 274m) ref. black 1 0 0 1 0 0 pll path. 1 0 0 1 0 1 eq path. 1 0 0 1 1 0 colour bars 1 0 0 1 1 1 1125 line, 74.25 mhz, 25 frame interlaced component (smpte 274m) ref. black 1 0 1 0 0 0 pll path. 1 0 1 0 0 1 eq path. 1 0 1 0 1 0 colour bars 1 0 1 0 1 1 1125 line, 74.25 mhz, 25 frame interlaced component (smpte 295m) ref. black 1 0 1 1 0 0 pll path. 1 0 1 1 0 1 eq path. 1 0 1 1 1 0 colour bars 1 0 1 1 1 1 1125 line, 74.25 mhz, 30 frame progressive component (smpte 274m) ref. black 1 1 0 0 0 0 pll path. 1 1 0 0 0 1 eq path. 1 1 0 0 1 0 colour bars 1 1 0 0 1 1 1125 line, 74.25 mhz, 25 frame progressive component (smpte 274m) ref. black 1 1 0 1 0 0 pll path. 1 1 0 1 0 1 eq path. 1 1 0 1 1 0 colour bars 1 1 0 1 1 1 1125 line, 74.25 mhz, 24 frame progressive component (smpte 274m) ref. black 1 1 1 0 0 0 pll path. 1 1 1 0 0 1 eq path. 1 1 1 0 1 0 (1) note: bist test patterns for sd are: ntsc 4x3 colour bars and pal 4x3 pll pathological. 26 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 table 5. test pattern selection codes (1) (continued) test pattern select word bits > bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 colour bars 1 1 1 0 1 1 750 line, 74.25 mhz, 60 frame progressive component (smpte 296m) ref. black 1 1 1 1 0 0 pll path. 1 1 1 1 0 1 eq path. 1 1 1 1 1 0 colour bars 1 1 1 1 1 1 525 line, 30 frame, 27 mhz, ntsc 4x3 (smpte 125m) ref. black 0 0 0 0 0 0 pll path. 0 0 0 0 0 1 eq path. 0 0 0 0 1 0 colour bars (sd bist) 0 0 0 0 1 1 625 line, 25 frame, 27 mhz, pal 4x3 (itu-t bt.601) ref. black 0 1 0 0 0 0 pll path. (sd bist) 0 1 0 0 0 1 eq path. 0 1 0 0 1 0 colour bars 0 1 0 0 1 1 525 line, 30 frame, 36 mhz, ntsc 16x9 (smpte 125m) ref. black 0 0 0 1 0 0 pll path. 0 0 0 1 0 1 eq path. 0 0 0 1 1 0 colour bars 0 0 0 1 1 1 625 line, 25 frame, 36 mhz, pal 16x9 (itu-t bt.601) ref. black 0 1 0 1 0 0 pll path. 0 1 0 1 0 1 eq path. 0 1 0 1 1 0 colour bars 0 1 0 1 1 1 525 line, 30 frame, 54 mhz (ntsc) ref. black 0 0 1 0 0 0 pll path. 0 0 1 0 0 1 eq path. 0 0 1 0 1 0 colour bars 0 0 1 0 1 1 625 line, 25 frame, 54 mhz (pal) ref. black 0 1 1 0 0 0 pll path. 0 1 1 0 0 1 eq path. 0 1 1 0 1 0 colour bars 0 1 1 0 1 1 video info 0 register (address 0eh) re-synchronization of the parallel video output data with the parallel rate clock is controlled by the functions framing enable , framing mode and nsp . for operating details about these control bits, refer to the preceeding section about format registers 0 and 1 and the format mode bit. framing enable may be assigned as an input on the multi-function i/o port. the nsp (new sync position) bit indicates that a new or out-of-place trs character has been detected in the input data. this bit is set to a logic-1 and remains set for at least one horizontal line period or unless re-activated by a subsequent new or out-of-place trs. it is reset by an eav trs character. the eav (end of active video) and sav (start of active video) bits track the occurrence of the corresponding trs characters. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 27 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com the lock detect is a logic-1 when the loop is locked and the cdr has acquired a phase of the incoming serial data. this bit may be programmed as an output on the multi-function i/o bus. this bit is mapped to i/o port bit 4 in the default condition. the vpg filter enable bit when set enables operation of the video pattern generator filter. operation of this filter causes the insertion of transition codes in the chroma and luma data of colour bar test patterns where these patterns change from one bar to the next. this filter reduces the magnitude of out-of-band frequency products which are produced by abrupt transitions in the chroma and luma data when fed to d-to-a converters and picture monitors. the LMH0031 incorporates circuitry that implements a method for handling data that has been subjected to lsb dithering . data from the de-scrambler is routed for de-dithering. control of this circuitry is via the de-dither enable bit in the video info 0 control register. recovery of data that has been dithered during the vertical blanking interval can be selectively enabled by use of the v de-dither enable bit in the video info 0 control register. the initial condition of de-dither enable and v de-dither enable is off. video control 0 (register address 55h) the external v clk bit is a special application function which enables use of an external vcxo as a substitute for the internally generated v clk . additional circuitry is enabled within the LMH0031 which provides phase- frequency detection and control voltage output for the vcxo. an external loop filter and voltage amplifier are required to interface the control voltage output to the vcxo frequency control input. when this function is used, the r bb output function is changed from the bias supply output to the control voltage output of the phase- frequency detector. the v clk output changes function, becoming the input for the vcxo signal. use of this function and required external support circuitry is explained in the application information section. the sync detect enable bit, when set, enables detection of trs characters. this bit is normally set (on). the lsb clip enable bit, when set, causes the two lsbs of trs characters to be set to 00b as described in itu-r bt.601. this function is normally set (on). the nrzi enable bit, when set, enables data to be converted from nrzi to nrz. this bit is normally set (on). the de-scramble enable bit, when set, enables de-scrambling of the incoming data according to requirements of smpte 259m or smpte 292m. this bit is normally set (on). caution the default state of this register is 36h. if any of the normal operating features of the descrambler are turned off, this register ? s default data must be restored to resume normal device operation. reference clock register (address 67h) the reference clock register controls operation of the cdr reference clock source. the clken bit when reset to a logic-0 enables the oscillator signal to be used by the LMH0031 as a reference. the default state of this bit at power-on is enabled. in general, this function and bit should not be disabled. the int_osc en bit enables the internal crystal oscillator amplifier. by default this bit is a logic-0 and is therefore inactive at power-on. the device expects an external 27mhz reference reference clock source to be connected to the xtali/ext clk pin and activated at power-on. i/o pin 0 through 7 configuration registers (addresses 0fh through 16h) the i/o pin configuration registers are used to map individual bits of the multi-function i/o port to selected bits of the configuration and control registers. table 6 gives the pin select codes for the configuration and control register functions that may be mapped to the port. pin[n] select [5] controls whether the port pin is input or output. the port pin will be an input when this bit is set and an output when reset. input-only functions may not be configured as outputs and vice versa. the remaining five pin[n] select [4:0] bits identify the particular control register bit to be mapped. 28 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 example: program, via the ad port, i/o port bit 0 as output for the crc luma error bit in the control registers. 1. set anc/ ctrl to a logic-low. 2. set rd/ wr to a logic-low. 3. present 00fh to ad[9:0] as the i/o pin 0 config register address. 4. toggle a clk . 5. present 310h to ad[9:0] as the register data, the bit address of the crc luma error bit in the control registers. 6. toggle a clk . table 6. control register bit, pin[n] sel[5:0] codes for i/o port pin mapping (1) pin[n] sel[5:0] codes i/p or register bit power-on status o/p [5] [4] [3] [2] [1] [0] hex reserved 0 0 0 0 0 0 00 o/p ff flag error 0 0 0 0 0 1 01 o/p ap flag error 0 0 0 0 1 0 02 o/p anc flag error 0 0 0 0 1 1 03 o/p crc error (sd/hd) 0 0 0 1 0 0 04 o/p i/o port bit 5 addresses 05h and 06h are reserved anc fifo 90% full 0 0 0 1 1 1 07 o/p short msg detect 0 0 1 0 0 0 08 o/p full msg avail 0 0 1 0 0 1 09 o/p addresses 0ah through 0ch are reserved sav 0 0 1 1 0 1 0d o/p eav 0 0 1 1 1 0 0e o/p i/o port bit 7 nsp 0 0 1 1 1 1 0f o/p crc luma error 0 1 0 0 0 0 10 o/p crc chroma error 0 1 0 0 0 1 11 o/p f 0 1 0 0 1 0 12 o/p i/o port bit 0 v 0 1 0 0 1 1 13 o/p i/o port bit 1 h 0 1 0 1 0 0 14 o/p i/o port bit 2 format[0] 0 1 0 1 0 1 15 o/p format[1] 0 1 0 1 1 0 16 o/p format[2] 0 1 0 1 1 1 17 o/p format[3] 0 1 1 0 0 0 18 o/p format[4] 0 1 1 0 0 1 19 o/p i/o port bit 3 (sd/hd) fifo full 0 1 1 0 1 0 1a o/p fifo empty 0 1 1 0 1 1 1b o/p i/o port bit 6 lock detect 0 1 1 1 0 0 1c o/p i/o port bit 4 pass/fail 0 1 1 1 0 1 1d o/p fifo overrun 0 1 1 1 1 0 1e o/p anc chksum error 0 1 1 1 1 1 1f o/p edh force 1 0 0 0 0 0 20 i/p test pattern select[0] 1 0 0 0 0 1 21 i/p test pattern select[1] 1 0 0 0 1 0 22 i/p test pattern select[2] 1 0 0 0 1 1 23 i/p test pattern select[3] 1 0 0 1 0 0 24 i/p test pattern select[4] 1 0 0 1 0 1 25 i/p test pattern select[5] 1 0 0 1 1 0 26 i/p (1) note: all lvcmos inputs have internal pull-down devices except vclk and aclk. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 29 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com table 6. control register bit, pin[n] sel[5:0] codes for i/o port pin mapping (1) (continued) pin[n] sel[5:0] codes i/p or register bit power-on status o/p [5] [4] [3] [2] [1] [0] hex edh enable 1 0 0 1 1 1 27 i/p tpg enable 1 0 1 0 0 0 28 i/p addresses 29h through 2bh are reserved vpg filter enable 1 0 1 1 0 0 2c i/p de-dither enable 1 0 1 1 0 1 2d i/p framing enable 1 0 1 1 1 0 2e i/p fifo extract enable 1 0 1 1 1 1 2f i/p pin descriptions pin name description 1 ad9 ancillary data output, control data input 2 ad8 ancillary data output, control data input 3 ad7 ancillary data output, control data input 4 ad6 ancillary data output, control data input 5 ad5 ancillary data output, control data input 6 v ssd negative power supply input (2.5v supply, digital logic) 7 ad4 ancillary data output, control data input 8 ad3 ancillary data output, control data input 9 ad2 ancillary data output, control data input 10 ad1 ancillary data output, control data input 11 ad0 ancillary data output, control data input 12 v ddd positive power supply input (2.5v supply, digital logic) 13 a clk ancillary/control clock input 14 io7 multi-function i/o port 15 io6 multi-function i/o port 16 io5 multi-function i/o port 17 io4 multi-function i/o port 18 io3 multi-function i/o port 19 io2 multi-function i/o port 20 v ssio negative power supply input (3.3v supply, i/o) 21 dv19 parallel video output (hd=luma) 22 dv18 parallel video output (hd=luma) 23 dv17 parallel video output (hd=luma) 24 dv16 parallel video output (hd=luma) 25 dv15 parallel video output (hd=luma) 26 v ddio positive power supply input (3.3v supply, i/o) 27 dv14 parallel video output (hd=luma) 28 dv13 parallel video output (hd=luma) 29 dv12 parallel video output (hd=luma) 30 dv11 parallel video output (hd=luma) 31 dv10 parallel video output (hd=luma) 32 v ssd negative power supply input (2.5v supply, digital logic) 33 v ddd positive power supply input (2.5v supply, digital logic) 34 dv9 parallel video output (hd=chroma, sd=luma & chroma) 35 dv8 parallel video output (hd=chroma, sd=luma & chroma) 36 dv7 parallel video output (hd=chroma, sd=luma & chroma) 30 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 pin descriptions (continued) pin name description 37 dv6 parallel video output (hd=chroma, sd=luma & chroma) 38 dv5 parallel video output (hd=chroma, sd=luma & chroma) 39 v ssd negative power supply input (2.5v supply, digital logic) 40 dv4 parallel video output (hd=chroma, sd=luma & chroma) 41 dv3 parallel video output (hd=chroma, sd=luma & chroma) 42 dv2 parallel video output (hd=chroma, sd=luma & chroma) 43 dv1 parallel video output (hd=chroma, sd=luma & chroma) 44 dv0 parallel video output (hd=chroma, sd=luma & chroma) 45 io1 multi-function i/o port 46 io0 multi-function i/o port 47 v ssio negative power supply input (3.3v supply, i/o) 48 v ddio positive power supply input (3.3v supply, i/o) 49 reset manual reset input (high true) 50 v clk parallel video data clock output 51 v ddpll positive power supply input (2.5v supply, pll) 52 v sspll negative power supply input (2.5v supply, pll) 53 r ref current reference resistor 54 r bb sdi bias supply resistor 55 v sssi negative power supply input (3.3v supply, serial input) 56 sdi serial data complement input 57 sdi serial data true input 58 v ddsi positive power supply input (3.3v supply, serial input) 59 v ssio negative power supply input (3.3v supply, i/o) 60 xtali/ext clk crystal or external 27mhz clock input 61 xtalo crystal (oscillator output) 62 v ddd positive power supply input (2.5v supply, digital logic) 63 anc/ ctrl ancillary/control data port function control input 64 rd/ wr ancillary/control data port read/write control input copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 31 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com application information a typical application circuit for the LMH0031 is shown in the application circuit diagram. this circuit demonstrates the capabilities of the LMH0031 and allows its evaluation in a native configuration. an assembled demonstration board is available, part number sd131evk. the board may be ordered through any of ti's sales offices. complete circuit board layouts and schematics for the sd131evk are available on ti's web site. for latest availability information, please see: www.ti.com/appinfo/interface. pcb layout and power system bypass recommendations circuit board layout and stack-up for the LMH0031 should be designed to provide noise-free power to the device. good layout practice also will separate high frequency or high-level inputs and outputs from low-level inputs to minimize unwanted stray noise pickup, feedback and interference. power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. this increases the intrinsic capacitance of the pcb power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. external bypass capacitors should include both rf ceramic and tantalum electrolytic types. rf capacitors may use values in the range 0.01 f to 0.1 f. tantalum capacitors may be in the range 2.2 f to 10 f. voltage rating for tantalum capacitors should be at least 5x the power supply voltage being used. it is recommended practice to use two vias at each power pin of the LMH0031 as well as all rf bypass capacitor terminals. dual vias reduce the interconnect inductance by up to half, thereby extending the effective frequency range of the bypass components. the outer layers of the pcb may be flooded with additional v ss (ground) plane. these planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. naturally, to be effective, these planes must be tied to the v ss power supply plane at frequent intervals with vias. frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. the planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. in especially noisy power supply environments, such as is often the case when using switching power supplies, separate filtering may be used at the LMH0031's pll and serial input power pins. the LMH0031 was designed for this situation. the i/o, digital section, pll and serial input power supply feeds are independent (see table and block diagram for details). supply filtering may take the form of l-section or pi-section, l-c filters in series with these v dd inputs. such filters are available in a single package from several manufacturers. device power supplies must be either sequenced as described in power supplies, power-on-reset and reset input and ideally should be applied simultaneously as from a common source. maintaining output data integrity the way in which the trs and other video data characters are specified and are therefore output in parallel form can result in the simultaneous switching of many of the LMH0031 ? s cmos outputs. such switching can lead to the production of output high level droop or low level ground bounce. given in the specifications, v olp is the peak output low voltage or ground bounce and v ohv is the lowest output high voltage or output droop that may occur under dynamic simultaneous output switching conditions. v ohv and v olp are measured with respect to reference ground. careful attention to pcb layout, power pin connections to the power planes and timing of the output data clocking can reduce these effects. consideration must also be given to the timing allocated to external circuits which sample the outputs. the effects of simultaneous output switching on output levels may be minimized by adopting good pcb layout and data output timing practices, especially critical at hd data rates. the power pins feeding the i/o should have low inductance connections to the power and ground planes. it is recommended that these connections use at least two vias per power or ground pin. short interconnecting traces consistent with good layout practices and soldering rules must be used. sampling or clocking of data by external devices should be so timed as to take maximum advantage of the steady-state portion of the parallel output data interval. the LMH0031 is designed so that video data will be stable at the positive-going transition of v clk . data should not be sampled close to the data transition intervals associated with the negative-going clock edge. the specified propagation delay and clock to data timing parameters must be observed. when data is being sampled from the video data port together with the anc port and/or i/o port, it is recommended that the sampling clocks be synchronized with the video clock, v clk , to minimize possible effects from ground bounce or output droop on sampled signal levels. 32 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 processing non-supported raster formats the number and type of hd raster formats has proliferated since the LMH0031 was designed. though not specifically capable of fully or automatically processing these new formats, the LMH0031 may still be capable of deserializing them. the user is encouraged to experiment with processing these formats, keeping in mind that the LMH0031 has not been tested to handle formats other than those detailed in table 4 . therefore, the results from attempts to process non-supported formats is not ensured. the following guidelines concerning device setup are provided to aid the user in configuring the LMH0031 to attempt limited processing of these other raster formats. in general, the device is configured to defeat its automatic format detection function and to limit operation to a general hd format. (the user should consult table 4 for guidance on the format groups similar to the non- supported one to be processed). since most non-supported formats are in the hd group, the LMH0031 should be configured to operate in hd-only mode by setting bit-5 of the format 0 register (address 0bh). also, the device should be further configured by loading the format set[4:0] bits of this register with the general hd sub-format code. in addition, since control data is being written to the port, ad[9:8] must be driven as 11b. the complete data word for this general hd sub-format code with hd-only bit set is 33fh. since this format differs from those in the table, the eav/sav indicators are disabled. without these indicators, line numbering and crc processing are disabled and anc data extraction will not function. output video chroma and luma data will be word-aligned. post-processing of the parallel data output from the LMH0031 will be needed to implement crc checking or line number tracking. using external vcxo for vclk the external v clk bit of video control 0 (register address 55h) is a special application function which enables use of an external vcxo as a substitute for the internally generated v clk . additional circuitry is enabled within the LMH0031 which provides phase-frequency detection and control voltage output for the vcxo. an external loop filter and voltage amplifier are required to interface the control voltage output to the vcxo frequency control input. when this function is used, the r bb output function is changed from the bias supply output to the control voltage output of the phase-frequency detector. the v clk output changes function, becoming the input for the vcxo signal. figure 8 shows an example using dual vcxos for v clk to handle both standard and high definition video. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 33 product folder links: LMH0031
LMH0031 snls218a ? january 2006 ? revised april 2013 www.ti.com figure 8. using dual vcxos for vclk example the control voltage output from r bb is externally filtered by the loop filter consisting of a 22.1k ? resistor in series with a 10nf capacitor, combined in parallel with a 100pf capacitor. this gives a loop bandwidth of 1.5khz. since the control voltage is limited to around 2.1v, it requires a level shifter to get the entire pull range on the vcxo. ti's lmc7101 is recommended with 100k ? and 182k ? resistors as shown in figure 8 to provide a gain of 1.55, sufficient to drive a 3.3v vcxo. recommended vcxos from saronix (141 jefferson drive, menlo park, ca 94025, usa) include the st1308aab-74.25 for high definition and the st1307bab-27.00 for standard definition. dual vcxos require some supporting logic to select the appropriate vcxo. this requires the use of format[4] (sd/hd) and lock detect , which are mapped at power-on to i/o port bit 3 and i/o port bit 4, respectively. these two signals pass through an and gate (fairchild semiconductor's nc7sz08 or similar). its output is high when both lock detect and format[4] are high, which indicates a valid high-definition signal is present. the vcxos are buffered to control the transition times and to allow easy selection. the output of the and gate is used to control the output enable (oe) function of the buffers. the 74.25mhz vcxo is buffered with the nc7sz126 with the and gate output connected to the oe pin of the nc7sz126, and the 27.00mhz vcxo is buffered with the nc7sz125 with the and gate output connected to the oe pin of the nc7sz125. this circuit uses the 27.00mhz vcxo as default and enables the 74.25mhz vcxo when a valid high-definition signal is present. the outputs from the buffers are daisy-chained together and sent to the LMH0031's v clk in addition to other devices, such as the lmh0030 serializer. 34 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: LMH0031 + - 100 k : 182 k : v ctrl f out lmc7101 +3.3v v ctrl f out +3.3v nc7sz126 74.25 mhz vcxo 27.00 mhz vcxo LMH0031 r b b r ref v clk 22.1 k : 100 pf 10 nf 4.75 k : dv[19:0] to other logic or serializer caution! read text before using this circuit. nc7sz125 nc7sz08 clc031 io3 - sd/hd clc031 io4 - lock detect oe oe 22.1 : 22.1 :
LMH0031 www.ti.com snls218a ? january 2006 ? revised april 2013 revision history changes from original (april 2013) to revision a page ? changed layout of national data sheet to ti format .......................................................................................................... 34 copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 35 product folder links: LMH0031
package option addendum www.ti.com 24-nov-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples LMH0031vs nrnd tqfp pag 64 160 tbd call ti call ti 0 to 70 l031 LMH0031vs/nopb active tqfp pag 64 160 green (rohs & no sb/br) cu sn level-3-260c-168 hr 0 to 70 l031 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 24-nov-2013 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
mechanical data mtqf006a january 1995 revised december 1996 post office box 655303 ? dallas, texas 75265 pag (s-pqfp-g64) plastic quad flatpack 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 4040282 / c 11/96 gage plane 33 0,17 0,27 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
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